Present complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. The extensive demand for dynamic random access memory circuits requires an optimal balance between minimum feature sizes and the inherent defect density of the process in order to maximize yield. The trend in dynamic random access memory design is to improve yield beyond that afforded by minimal defect density. This is accomplished by the addition of spare elements that may be programmed to replace defective array elements and thereby improve yield.
Memory circuits are often divided into partitions or blocks that may be activated individually or as a group of blocks to conserve power or facilitate parallel test. Speed limitations and complexity compromised the effectiveness of previous spare circuits designed for operation with partitioned memory circuits. This imposed a speed penalty on the entire memory circuit, because its access time was characterized by the slowest element. In, U.S. Pat. No. 5,208,776, entitled PULSE GENERATION CIRCUIT, Nasu et al disclose a spare circuit in FIGS. 12-19 for operation with a memory circuit having four partitions. Fuse programmable circuits, storing an internal address (FIG. 14), apply either true or complementary external address signals to one of twelve first-stage NOR decoders (FIG. 15) in response to the state of each fuse. The output of each first-stage NOR decoder is routed to each of four second-stage NOR decoders (FIG. 18), corresponding to the four quadrants or blocks. The output of the second-stage NOR decoder enables the spare element (FIG. 19) and disables the normal element (FIG. 12).
There are numerous complex features in the spare circuit disclosed by Nasu. Twelve first-stage decoder outputs must be buffered and routed to each of the four remote second-stage decoders. Each second-stage decoder requires one fuse for each first-stage decoder. Fuses of every second-stage decoder corresponding to a first-stage decoder must be blown except where replacement is desired. These complexities quickly become impractical with an increasing number of first-stage decoders and blocks. For example, for twenty-four first-stage decoders and eight blocks, the circuit disclosed by Nasu would require routing twenty-four first-stage decoder outputs to each of the eight blocks and programming a fuse in seven second-stage decoders for each single-block repair. Additionally, the speed penalty of buffering and series-connected NOR decoders limits the effectiveness of the memory circuit.